Microprocessor Architectures - RISC, CISC and DSP

Microprocessor Architectures - RISC, CISC and DSP

von: Steve Heath

Elsevier Reference Monographs, 2014

ISBN: 9781483295534 , 415 Seiten

2. Auflage

Format: PDF

Kopierschutz: DRM

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Microprocessor Architectures - RISC, CISC and DSP


 

Front Cover

1

Microprocessor Architectures RISC, CISC and DSP

4

Copyright Page

5

Table of Contents

6

Preface

14

Acknowledgements

16

Chapter 1. Complex instruction set computers

18

8 bit microprocessors: the precursors of CISC

18

8 bit microprocessor register models

20

Requirements for a new processor architecture

26

Software compatibility

27

Enter the MC68000

29

Complex instructions, microcode and nanocode

30

The MC68000 hardware

32

Typical system

41

Multitasking operating systems

49

Context switching, task tables and kernels

51

Start of a revolution

55

The MC68010 virtual memory processor

56

Virtual memory support

56

Virtual machine support

59

MC68010 SUPERVISOR resource

60

Other improvements

61

The MC68008

62

The story continues

63

Chapter 2. 32 bit CISC processors

64

Enter HCMOS technology

64

Architectural challenges

65

The MC68020 32 bit performance standard

67

The internal design philosophy

68

The programmer's model

70

Dynamic bus sizing

74

On chip instruction cache

76

Debugging support

80

Coprocessor interface

82

MC68881 and MC68882 floating point coprocessors

84

The MC68651 paged memory management unit (PMMU)

87

The MC68030: the first commercial 50 MHz processor

88

Memory management

91

Chapter 3. The RISC challenge

94

The 80/20 rule

94

The initial RISC research

95

The Berkeley model

96

The Stanford model

97

The catalysts

97

The M88000 family

98

M88000 concurrent functional units

100

Multiple execution units and optimisation

101

Scoreboarding

103

Delayed branching

105

The MC88100 programming model

106

Handling exceptions

107

The MC88100 instruction set

108

Addressing data

109

Fetching data

109

MC88100 external functions

111

Single-cycle memory buses

113

MC88200 cache MMU

114

Memory management functions

115

Cache coherency

116

The MBUS protocol

117

M88000 master / checker fault tolerance

119

Future enhancements

119

Chapter 4. RISC wars

121

RISC versus CISC

121

Enter the MC68040

122

Superscalar alternatives

131

Superpipelining

132

Very long instruction word

133

Superscalar principles

134

Controlling multiple instructions per clock

136

Software control

138

The MC88110

139

Enter the PowerPC

143

The PowerPC architectural model

144

Execution pipelines

147

Branch delays

153

Branch folding

155

Static branch prediction

157

Branch prediction cache

158

Register renaming

159

The MPC601 block diagram

161

The MPC603 block diagram

163

Chapter 5. Digital signal processors

165

Processor requirements

169

The DSP56000 family

170

Basic architecture

170

The programming model

178

The instruction set

180

Arithmetic and logical instructions

180

Bit manipulation

182

Loop control

182

MOVE commands

183

Program control

183

Instruction format

184

Using special addressing and loop modes

184

Internal parallelism

185

Architectural differences

186

DSP96000 — combining integration and performance

186

OnCE — a new approach to emulation

188

Chapter 6. Memory, memory management and caches

189

Achieving processor throughput

189

Partitioning the system

191

Shadow RAM

192

DRAM versus SRAM

193

Optimising the DRAM interface

194

Page mode operation

194

Page interleaving

195

Alternative memory systems

197

Burst mode SRAM

197

Big vs. little endian organization

199

Memory management

201

Disadvantages of memory management

203

Segmentation and paging

204

Multitasking and user / supervisor conflicts

209

Table walking and RISC architectures

211

Instruction continuation versus restart

216

Memory management and DSP

216

Cache memory

217

Cache size and organization

217

Optimising line length and cache size

222

Logical versus physical caches

223

Unified versus Harvard caches

224

Cache coherency

225

Case 1: write through

226

Case 2: write back

227

Case 3: no caching of write cycles

228

Case 4: write buffer

228

Bus snooping

228

The MESI protocol

234

The MEI protocol

235

Streaming and CWF (critical word first)

236

Cache control instructions

238

Implementing memory systems

239

Secondary or level 2 caches

239

Conclusions

240

Chapter 7. Real-time software, interrupts and exceptions

241

What is real-time software

241

Responding to an interrupt

242

Improving performance

245

Interrupting CISC and RISC processors

245

RISC interrupt service routines

246

Improving software performance

248

Addressing data

248

Fetching data

248

Testing data

250

Saving and restoring register sets

251

Interrupting the DSP56000

252

Diadic versus triadic instruction sets

253

Instruction restart versus instruction continuation

254

External memory and real-time performance

254

Register windowing

256

Combining architectures

256

The M68300 family

258

Software considerations

260

Combining DSP processors

261

Conclusions

264

Chapter 8. Multiprocessing

265

SISD — single instruction, single data

265

SIMD — single instruction, multiple data

266

MIMD — multiple instruction, multiple data

267

MISD — multiple instruction, single data

268

Constructing a MIMD architecture

268

Processor bandwidths

270

Profiling

271

Cost of memory access

272

Fault tolerant systems

275

Single- and multiple-threaded operating systems

278

Chapter 9. Application examples

281

MC68020 and MC68030 design techniques for high reliability applications

281

Upgrading 8 bit systems

291

Transparent update techniques for digital filters using the DSP56000

296

Motor and servo control

299

Improved SRAM interfaces

305

Chapter 10. Semiconductor technology

312

Silicon technology

312

CMOS and bipolar technology

314

Fabrication technology

316

Packaging

317

Processor technology

320

Memory technology

320

Science fiction or not

322

Chapter 11. The changing design cycle

323

The shortening design cycle

323

The double-edged sword of technology

325

Make versus buy

325

Simulation versus emulation

331

Chapter 12. The next generations

344

MC68000 — superscalar CISC

344

The MPC604

345

The future for CISC

346

An alternative direction — system integration

347

The M68300 family

347

Improving the instruction set

351

Summary

353

Chapter 13. Selecting a micro-processor architecture

355

Meeting performance needs

355

Choice of platforms

355

Anticipating future needs

356

Software support

356

Development support

357

Standards

360

Built-in obsolescence

361

Market changes

361

Considering all the options

362

Appendices

363

A 'Lies, damn lies and benchmarks'

363

B Alternative micro-processor architectures

369

Index

400